1) Field of the Invention
The invention is in the fields of Semiconductor Structures and Semiconductor Equipment.
2) Description of Related Art
For the past several years, the performance and capabilities of integrated circuits (ICs), e.g. logic circuits for computation and memory circuits for information storage, have been greatly enhanced by scaling the features of semiconductor structures to ever smaller dimensions. However, it is seldom the case that the equipment and processes used to fabricate ICs scale without issue. Continued advances in both semiconductor process technologies as well as in the equipment used to carry out such processes has ensured survival of the relentless pursuit of scaling by the Semiconductor Industry.
In order to pattern semiconductor stacks into meaningful structures, a lithography/etch process is typically employed. State-of-the-art etch processes include etching a semiconductor stack with a system comprising an ionized gas, i.e. a plasma. Plasma etch processing may be particularly useful for etching multiple adjacent structures with fine features. However, as demands on feature size and spacing become more stringent, limitations of the plasma etch process have revealed themselves.
One potential limitation of plasma etching may be with respect to the fabrication of an IC with variable spacing between various semiconductor structures within a single sample. For example, the etch rate may exhibit a dependence on pattern density, a phenomenon referred to as “micro-loading.” At very small dimensions, and particularly in high aspect ratio regimes, the etch rate of a material that has been patterned with a high density (i.e. smaller spacings between features) may be slower than the etch rate of the same material patterned with a low density (i.e. larger spacings between features). Thus an “over-etch” may be required to fully etch all of the various structures within a single sample, i.e. the areas that are first to completely etch continue to be exposed to the etch process while areas that have not completely etched undergo completion of the etch process. In some cases, this over-etch may have a detrimental impact on the resultant semiconductor structures.
Referring to FIG. 1, a plot is provided correlating the etch rate of a particular semiconductor material with the density (i.e. spacings between features) of various semiconductor structures in a single sample in which micro-loading occurs. As indicated by the decreasing slope of the correlation line, the etch rate decreases with increasing density. Referring to FIG. 2A, a semiconductor stack 200 comprises a substrate 202, a semiconductor layer 204 and a mask 206. Referring to FIG. 2B, the pattern of mask 206 is etched into semiconductor layer 204 with a plasma etch process. Micro-loading can occur during the etch process of semiconductor stack 200, such that semiconductor layer 204 etches faster in low density region 208 than in medium density region 210 and high density region 212, as depicted in FIG. 2B. Referring to FIG. 2C, the etch process performed on semiconductor stack 200 is completed in low density region 208 prior to completion in medium density region 210 and in high density region 212. Thus, the structures in low density region 208 are exposed to an over-etch while the etch is completed in regions of higher density. Referring to FIG. 2D, during the over-etch, some detrimental undercutting 214 may occur on structures in regions of lower density. The undercutting may vary with the density, depending on the extent of over-etch that a particular region experiences, as depicted in FIG. 2D.
Thus, a method for etching semiconductor structures is described herein, along with a system within which the method may be conducted.